The present invention relates to the field of semiconductor memory devices. More particularly, this invention relates to a memory device which includes a sense amplifier circuit that reduces access device leakage during active refresh.
Semiconductor memory devices, such as dynamic random access memory (DRAM) devices, typically store data in an array of memory cells. Each cell in the array stores a single bit of data (i.e., a logic one or zero) as a charge on a capacitor. For example, referring to FIG. 1, a DRAM memory cell or memory bit 100 consists of one MOS transistor 102 and one storage capacitor 104xe2x80x94accordingly referred to as a one-transistor one-capacitor (1T1C) cell. Memory bit transistor 102 operates as a switch, interposed between the memory bit capacitor 104 and a digit or bit line 106. Memory bit 100 is capable of holding a single piece of binary information as stored electric charge in capacitor 104. Given a bias voltage of Vcc/2 on capacitor 104""s common node, a logic one level is represented by +Vcc/2 volts across the capacitor, and a logic zero is represented by xe2x88x92Vcc/2 volts across the cell capacitor. Thus, the potential at node 110 typically equals Vcc for logic one, and ground for logic zero.
Digit line 106 consists of a conductive trace or line connected to a multitude of memory bit transistors for a multitude of memory cells in an array. Generally, either metal or silicided/polycided polysilicon forms the conductive line. Due to the large quantity of attached memory bits, its physical length, and its proximity to other features, digit line 106 is very capacitive. For instance, a typical value for digit line capacitance on a 0.35 xcexcm process might be around 300 fF. Digit line capacitance is an important parameter since it dictates many other aspects of the memory design.
Memory bit transistor 102""s gate terminal connects to a word line (row line) 108. Word line 108, which also connects to a multitude of memory bits or memory cells, consists of an extended segment of the same polysilicon that is used to form the transistor 102""s gate. Word line 108 is formed so as to be physically orthogonal to digit line 106. A memory array 200, as in FIG. 2, is created by tiling a selected quantity of memory bits 100 together so that memory bits 100 along a given digit line 106 do not share a common word line 108, and bits 100 along a common word line 108 do not share a common digit line 106. In the layout of FIG. 2, memory bits are paired to share a common contact to the digit line, which reduces the array size.
Referring to FIG. 2, assume that the cell capacitors have logic one levels (+Vcc/2) stored on them. The digit lines D0, D1 . . . DN and D0*, D1* . . . DN* are initially equilibrated at Vcc/2 volts. All word lines WL0, WL1 . . . WLM are initially at 0 volts, which turns off the memory bit transistors. To read memory bit 1, word line WL0 transitions to a voltage that is at least one voltage threshold Vth above Vcc. This elevated word line voltage level is referred to as Vccp or Vpp. When the word line voltage exceeds one Vth above the digit line voltage (Vcc/2 in this example) and the memory bit transistor turns on, the memory bit capacitor will begin to discharge onto the digit line. Essentially, reading or accessing a DRAM cell results in charge sharing between the memory bit capacitor and the digit line capacitance. This sharing of charge causes the digit line voltage to either increase for a stored logic one or decrease for a stored logic zero. A differential voltage (Vsignal) develops between the two digit lines. The magnitude of this signal voltage Vsignal is a function of the memory bit capacitance (Cmemory_bit), digit line capacitance (Cdigit), the memory bit""s stored voltage prior to the access (Vcell), and any noise terms Vnoise. For a design in which Vcell=1.65 V, Cmemory_bit=40 fF, Cdigit=300 fF and Vnoise=0, this yields a digit line change of Vsignal=194 mV. FIG. 3 provides a graph 300 with waveforms for the cell access operation just described.
After the cell access is complete, a sensing operation can commence. The reason for forming a digit line pair will now become apparent. FIG. 4 contains a schematic diagram for a simplified typical sense amplifier circuit 400. Circuit 400 consists of a cross-coupled NMOS transistor pair 402 forming an N-sense amplifier, and a cross-coupled PMOS transistor pair 404 forming a P-sense amplifier. The N-sense-amp common node is labeled NLAT* (for N-sense-amp LATch). Similarly, the P-sense-amp common node is labeled ACT (for ACTive pull-up). As shown in FIG. 5, NLAT* is biased to Vcc/2 volts and ACT is biased to Vss or ground. Since the digit line pair D0 and D0* are both initially at Vcc/2 volts, the N-sense-amp transistors are initially off due to zero Vgs potential. Similarly, both P-sense-amp transistors are initially off due to their positive Vgs potential. As discussed in the preceding paragraph, a signal voltage develops between the digit line pair D0 and D0* when the memory bit access occurs. While one digit line (D0) contains charge from the cell access, the other digit line (D0*) serves as a reference for the sensing operation. The sense amplifier firing generally occurs sequentially rather than concurrently. The N-sense-amp fires first and the P-sense-amp fires second. The N-sense amplifier is generally a better amplifier than the P-sense-amp because of the higher drive of NMOS transistors, and better Vth matching. This provides for better sensing characteristics and lower probability of errors. Dropping the NLAT* signal toward ground will fire the N-sense-amp. As the voltage between NLAT* and the digit line approaches Vth, the N-sense-amp transistor whose gate connection is to the higher voltage digit line will begin to conduct first. This conduction results in the discharge of the low voltage digit line toward the NLAT* voltage. Ultimately, the NLAT* voltage will reach ground, bringing the low voltage digit line with it. The other NMOS transistor of the N-sense-amp will not conduct since its gate voltage derives from the low voltage digit line, which is being discharged toward ground.
Shortly after the N-sense-amp fires, ACT will be driven toward Vcc volts. This activates the P-sense-amp that operates in a complementary fashion to the N-sense-amp. With the low voltage digit line approaching ground, a strong signal will exist to drive the appropriate PMOS transistor into conduction. This will charge the high voltage digit line toward ACT, ultimately reaching Vcc. Since the memory bit transistor 102 remains on during sensing, the memory bit capacitor 104 is charged to the NLAT* voltage level (for a stored logic zero) or the ACT voltage level (for a stored logic one). Thus, the voltage, and hence the charge, which the memory bit capacitor held prior to accessing will be restored to a full level. In other words, capacitor 104 will be charged to Vcc for logic one and ground for logic zero. This restoration of the charge on capacitor 104 can be referred to as a refresh operation.
For a memory write operation, the paired digit lines are charged to represent the data to be written into the memory cell. Referring back to FIG. 1, the word line 108 is activated to turn on the memory bit transistor 102 to connect the digit line 106 to the memory cell capacitor 104, thereby allowing write data on D0/D0* to charge the cell capacitor. It will be appreciated that the memory read/write operations have been described herein in a simplified manner and that such access operations include numerous additional steps known to those skilled in the art.
As illustrated by FIG. 5, when the memory bit being accessed stores a logic one, the low voltage digit line D0* will be discharged toward the NLAT* voltage during a sensing operation. Similarly, when the memory bit being accessed stores a logic zero, the low voltage digit line D0 will be discharged toward NLAT*. Thus, in either case, the refresh operation will result in the low voltage digit line being discharged toward ground. Therefore, the xe2x80x9czeroxe2x80x9d seen on the low voltage digit line during the refresh access will have a potential of zero (i.e., ground potential). Such a memory refresh access may be referred to in the art as a LRL or active refresh access.
Unfortunately, allowing the xe2x80x9czeroxe2x80x9d seen on the low voltage digit line during a refresh access to be discharged all the way down to ground results in a relatively large access device leakage on all cells not being accessed but sharing the grounded digit, and adversely effects refresh margin on a DRAM cell with a one written thereto. Therefore, what is needed is an improved method and apparatus for reducing access device leakage of a DRAM memory cell during a LRL refresh access, and for improving refresh margin on a DRAM cell with a one written thereto. There is further a need for an improved sense amplifier for use in a DRAM memory circuit that reduces access device leakage, and improves refresh margin on a memory cell with a one written thereto. Preferably, such an improved sense amplifier would provide these advantages without adversely affecting its lock.
In accordance with one aspect of the invention, a sense amplifier circuit includes a first amplifier circuit and a second amplifier circuit, each having a first node and a second node. The first amplifier circuit includes a pair of cross-coupled transistors of a first channel type, and the second amplifier circuit includes a pair of cross-coupled transistors of a second channel type. The sense amplifier circuit also includes a third transistor of the second channel type coupled between the first node of the first amplifier circuit and the first node of the second amplifier circuit, and a fourth transistor of the second channel type coupled between the second node of the first amplifier circuit and the second node of the second amplifier circuit.
In accordance with another aspect of the present invention, a sense amplifier circuit includes an N-sense amplifier circuit and a P-sense amplifier circuit, each of which has first and second nodes, a first P-channel transistor coupled between the first node of the N-sense amplifier circuit and the first node of the P-sense amplifier circuit, and a second P-channel transistor coupled between the second node of the N-sense amplifier circuit and the second node of the P-sense amplifier circuit.
These and various other features as well as advantages which characterize the present invention will be apparent to a person of ordinary skill in the art upon reading the following detailed description and reviewing the associated drawings.